Addressing Modes in 8086

Prepared by Saad Aslam

Addressing mode indicates a way of locating data or operands. Depending up on the
data type used in the instruction and the memory addressing modes, any instruction may
belong to one or more addressing modes or same instruction may not belong to any of the
addressing modes.
The addressing mode describes the types of operands and the way they are accessed for
executing an instruction. According to the flow of instruction execution, the instructions may be
categorized as
1. Sequential control flow instructions and
2. Control transfer instructions.
Sequential control flow instructions are the instructions which after execution, transfer
control to the next instruction appearing immediately after it (in the sequence) in the program. For
example the arithmetic, logic, data transfer and processor control instructions are Sequential
control flow instructions.
The control transfer instructions on the other hand transfer control to some predefined
address or the address somehow specified in the instruction, after their execution. For example
INT, CALL, RET & JUMP instructions fall under this category.
The addressing modes for Sequential and control flow instructions are explained as follows.
1. Immediate addressing mode:
In this type of addressing, immediate data is a part of instruction, and appears
in the form of successive byte or bytes.
Example: MOV AX, 0005H.
In the above example, 0005H is the immediate data. The immediate data may be 8- bit or 16-bit in
size.
2. Direct addressing mode:
In the direct addressing mode, a 16-bit memory address (offset) directly specified in the
instruction as a part of it.
Example: MOV AX, [5000H].
3. Register addressing mode:
In the register addressing mode, the data is stored in a register and it is referred using the
particular register. All the registers, except IP, may be used in this mode.
Example: MOV BX, AX
4. Register indirect addressing mode:
Sometimes, the address of the memory l o c a t i o n which contains data or operands is
determined in an indirect way, using the offset registers. The mode of addressing is known as
register indirect mode.
In this addressing mode, the offset address of data is in either BX or SI or DI Register. The
default segment is either DS or ES.
Example: MOV AX, [BX].
5. Indexed addressing mode:
In this addressing mode, offset of the operand is stored one of the index registers. DS & ES
are the default segments for index registers SI & DI respectively.
Example: MOV AX, [SI]
Here, data is available at an offset address stored in SI in DS.
6. Register relative addressing mode:
In this addressing mode, the data is available at an effective address formed by adding an
8-bit or 16-bit displacement with the content of any one of the register BX, BP, SI & DI in the default
(either in DS & ES) segment.
Example: MOV AX, 50H [BX]
7. Based indexed addressing mode:
The effective address of data is formed in this addressing mode, by adding content of a
base register (any one of BX or BP) to the content of an index register (any one of SI or DI). The
default segment register may be ES or DS.
Example: MOV AX, [BX][SI]
8. Relative based indexed:
The effective address is formed by adding an 8 or 16-bit displacement with the sum of
contents of any of the base registers (BX or BP) and any one of the index registers, in a default
segment.
Example: MOV AX, 50H [BX] [SI]
For the control transfer instructions, the addressing modes depend upon whether the
destination location is within the same segment or in a different one. It also depends upon the
method of passing the destination address to the processor. Basically, there are two addressing
modes for the control transfer instructions, viz. Inter segment and intra segment addressing modes.
If the location to which the control is to be transferred lies in a different segment
other than the current one, the mode is called intersegment mode. If the destination
location lies in the same segment, the mode is called intersegment mode.
Addressing Modes for control transfer instructions:
1. Intersegment
· Intersegment direct
· Intersegment indirect
2. Intrasegment
· Intrasegment direct
· Intrasegment indirect



1. Intersegment direct:
In this mode, the address to which the control is to be transferred is in a different segment.
This addressing mode provides a means of branching from one code segment to another code
segment. Here, the CS and IP of the destination address are specified directly in the instruction.
Example: JMP 5000H, 2000H; jump to effective address 2000H in segment 5000H.
2. Intersegment indirect:
In this mode, the address to which the control is to be transferred lies in a different
segment and it is passed to the instruction indirectly, i.e. contents of a memory block
containing four bytes, i.e. IP(LSB), IP(MSB), CS(LSB) and CS(MSB) sequentially. The
starting address of the memory block may be referred using any of the addressing modes,
except immediate mode.
Example: JMP [2000H].
Jump to an address in the other segment specified at effective address 2000H in DS.
3. Intrasegment direct mode:
In this mode, the address to which the control is to be transferred lies in the same
segment in which the control transfers instruction lies and appears directly in the
instruction as an immediate displacement value. In this addressing mode, the displacement
is computed relative to the content of the instruction pointer.
The effective address to which the control will be transferred is given by the sum
of 8 or 16 bit displacement and current content of IP. In case of jump instruction, if
the signed displacement (d) is of 8-bits (i.e. -128<d<+127), it as short jump and if it is of 16
bits (i.e. -32768<d<+32767), it is termed as long jump.
Example: JMP SHORT LABEL.
4. Intrasegment indirect mode:
In this mode, the displacement to which the control is to be transferred is in the
same segment in which the control transfer instruction lies, but it is passed to the
instruction directly. Here, the branch address is found as the content of a register or a
memory location.
This addressing mode may be used in unconditional branch instructions.
Example: JMP [BX]; Jump to effective address stored in BX.