SISO,SIPO Shift Registers-DLD

       Prepared by :Saad Aslam  

                                                                                 

       Shift Register

Ø  The Shift Register is another type of sequential logic circuit that can be used for the storage or transfer of data in the form of binary numbers.

Ø  This Sequential device loads the data present on its inputs and then moves or “Shifts” It to its output once every clock cycle,hence the name Shift Register.

Ø  Being a sequential logic ,it is not only affected by the present inputs ,but also, the past inputs.

Types of Shift Registers:

1.       Serial-In/Serial-Out(SISO)

2.       Serial-In/Parallel-Out(SIPO)

3.       Parallel-In/Serial-Out(PISO)

4.       Parallel-In/Parallel-Out(PIPO)

1.       Serial-In/Serial-Out(SISO)

Serial-In to Serial-Out(SISO) –the data is shifted serially “IN” and  serially “OUT” of the register, one bit at a time in either a left or right direction under clock control

             Let us assume that all the flip flops have just been RESET  and all the outputs are at logic level “0” ie no Serial output.If a logic “1” is connected to DATA input of first flip flop (FF-1) then on the first clock pulse the output of first flip flop(FF-1) will be set High to logic “1” with all the outputs stil remaining LOW at logic “0”.Assume now that Data input of FF-1 has returned LOW again to logic “0” giving us one data pulse or 0-1-0.

            The second clock pulse will change the logic of FF-1 to logic “0” and the output of second flip flop(FF-2) will set to High logic “1” as its  input D has the logic “1”.The logic “1” has now moved or been shifted from FF-1 to FF-2.

         When the third clock pulse arrives this logic “1” will shift from FF-2 to third flip flop (FF-3)  and the output of FF-3 will have logic “1” .This process will continue until the arrival of fifth clock pulse which sets all the outputs back to logic level “0”.

    The effect of each clock pulse is to shift the data contents of each stage one place to the right ,until the complete data value is stored in the register.This data value can now be read serially by the output of the last flip flop FF-4.

2.       Serial-IN/Parallel-Out(SIPO)

              Serial-In to Parallel-Out(SIPO)-the data is shifted serially “IN” and parallely “OUT” of the register, one bit at a time in either a left or right direction under clock control.

Block Diagram:

Working:

               It has same pattern as SISO but instead of having the output serially by the last flip flop  ,the outputs are taken by each flip flop at the end.Let us assume that all the flip flops have just been RESET  and all the outputs are at logic level “0” ie no parallel output.If a logic “1” is connected to DATA input of first flip flop (FF-1) then on the first clock pulse the output of first flip flop(FF-1) will be set High to logic “1” with all the outputs stil remaining LOW at logic “0”.Assume now that Data input of FF-1 has returned LOW again to logic “0” giving us one data pulse or 0-1-0.

            The second clock pulse will change the logic of FF-1 to logic “0” and the output of second flip flop(FF-2) will set to High logic “1” as its  input D has the logic “1”.The logic “1” has now moved or been shifted from FF-1 to FF-2.

         When the third clock pulse arrives this logic “1” will shift from FF-2 to third flip flop (FF-3)  and the output of FF-3 will have logic “1” .This process will continue until the arrival of fifth clock pulse which sets all the outputs back to logic level “0”.

    The effect of each clock pulse is to shift the data contents of each stage one place to the right ,until the complete data value is stored in the register.This data value can now be read directly from the outputs of all flip flops.